sequential logic发音

意思翻译

[计]时序逻辑；顺序逻辑；循序逻辑

相似词语短语

logic───n.逻辑；逻辑学；逻辑性

cartesian logic───笛卡尔逻辑

effectual logic───有效逻辑

sophism logic───诡辩逻辑

swirl logic───漩涡逻辑

circ logic───电路逻辑

logic puzzles───逻辑猜谜

chop logic───v.强词夺理；咬文嚼字；强词夺理；争辩

logic bomb───逻辑炸弹（程序）；[计]逻辑炸弹

双语使用场景

Sequential logic synthesis is an important part of RTL synthesis system design.───时序逻辑综合是RTL综合系统设计中的一个重要部分。

This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.───本实验指导书分为两大部分：组合逻辑，时序逻辑。

The second is where you have to integrate the loop closely with the sequential logic.───第二点是，人们必须将一些控制环与顺序逻辑控制更紧密地集成。

The race and hazard in the sequential logic circuit is quite essential and must be considered when designing logic circuit.───时序逻辑电路中的竞争冒险是电路设计中必须考虑到的重要方面。

This system uses the main techniques are: sequential logic circuit technology.───此系统使用的主要技术是：时序逻辑电路技术。

This method which is called tendency value table is applied to some sequential logic circuits.───本文还分析了开关对逻辑电路产生干扰的原因和抑制方法。

a complete line of equipment sintering automatic sequential logic process cycle time is not more than 95 seconds.───在线工艺设备完成一个烧结自动循环循序逻辑流程时间不大于95秒。

It is a sequential logic circuit; its outputs depend not only on the current input values, but also on how they have changed in the past.───这是一种时序电路，它的输出不仅依赖于当前的输入值，还与以前输入值是如何变化的有关。

英语使用场景

In the design of the sequential logic circuit, redundant state is used to assign the state, so the assignment is more consistent to the A -H rule, and simple sequential structure can be obtained.

The method modifies the normal sequential logic by adding additional shift function module to improve the controllability and the observability.

Sequential logic synthesis is an important part of RTL synthesis system design.

In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.

This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.

Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.

Flip - flops are a key component and memory cells of sequential logic circuit.