one clock信息详情

one clock发音

意思翻译

一个时钟

相似词语短语

clock───vt.记录;记时;n.(Clock)人名;(英)克洛克;n.时钟;计时器;vi.打卡;记录时间

twelveo clock───十二点钟

electric clock───[仪]电钟

pelvic clock───骨盆时钟

o clock───n.点钟

speaking clock───n.电话报时服务

sextant clock───六分仪钟

gpu clock───gpu时钟

mem clock───内存时钟

双语使用场景

Its first design was very simple and all instructions were completed in one clock cycle.───它的第一个设计非常简单,所有指令都在一个时钟周期内完成。

Underneath it all is one clock, the clock in the cell.───它下面只是一个时钟,一个细胞中的时钟。

There was one database, one server, and one clock.───有一个数据库、一台服务器和一个时钟。

This monolithic environment for an application eliminated any concern about which clock to use -- because there was only one clock.───对于一个应用程序的这个单块集成电路环境消除了使用哪个时钟的问题——因为只有一个时钟。

Within one clock cycle there are therefore two settling actions that have to be performed, as in the two-step architecture.───因此,在一个时钟周期内,像二阶结构一样,有两个予置动作必须执行。

One clock was in the shape of a cart with a horse and driver.───一座钟被建成有一人一马的马车形状。

but because all instructions completed in one clock cycle , it lacked floating - point and superscalar parallel processing ability.───但是由于所有的指令都必须在一个时钟周期内完成,因此其浮点运算和超量计算(并行处理)能力很差。

We have at least one clock in almost every room in the house.───我们的家中几乎每个房间都有一个时钟。

In my relativity theory i set up a clock at every point in space, but in reality i find it difficult to provide even one clock in my room.───在我的相对论中,我可以在空间的每一点放置一个时钟;但在现实世界里,我发现即使在我的房间放置一个始终都是困难的。

英语使用场景

The judges will start one clock at the moment a team member steps on the stage for the 5 minutes period, and another clock at the beginning ot the music for the 2 minutes performance period.

The judges will start one clock at the moment a team member steps on the stage for the 5 minutes period, and another clock at the beginning of the music for the 2 minutes performance period.

The default time slice is 10 ms (for one clock tick).

The conversion speed is improved through the reduction of the number of the clock phases required for one conversion and the time allocated for one clock phase.

In ASIC design, different modules often work in different frequency. Designing a pure, one clock synchronous design is luxury and impossible.