bit line发音

意思翻译

[电子]位线

相似词语短语

bit───adj.很小的；微不足道的；n.[计]比特（二进位制信息单位）；少量；马嚼子；辅币；老一套；一点，一块；adv.有点儿；相当；vt.咬（bite的过去式和过去分词）；vt.控制

bit by bit───一点儿一点儿地，逐渐地; 点点滴滴; 一点一滴；一点一点地

line line───线条线条

bit backup───位备份

bit into───咬进；啃

fillister bit───凹形钻头

df bit───测向钻头

casing bit───套管钻头

line───n.(Line)人名；(英)莱恩；(俄)利涅；vt.排成一行；划线于；以线条标示；使…起皱纹；vi.排队；站成一排；n.路线，航线；排；绳

双语使用场景

contact plug is electrically connected to the common doped region and the bit line is disposed over the substrate.───接触窗插塞电性连接至共用掺杂区域，且位线配置于基底上。

The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.───该半导体存储器件包含连接到一对位线的位线感测放大器。

Moreover, the resistive memory element is connected between the contact plug and the bit line.───此外，电阻式存储器元件连接于接触窗插塞与位线之间。

A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells.───位于绝缘层上的位线电连接到多个电阻存储器单元中的最后一个。

A first global bit line may be connected to a first one of the plurality of transistors.───与所述多个晶体管中的第一晶体管相连的第一全局位线；

The top electrode 15 itself can be used to constitute a bit line, or a separate bit line can be provided.───上电极15自身可以用来构成位线，或者可以设置独立的位线。

The SRAM memory means comprises a first pass-gate FET (T6) which is coupled between a first node (A) and a bit line-bar (BLB).───SRAM存储器装置包括耦合在第一节点（A）和位线条（BLB）之间的第一门FET（T6）。

The contact plug is electrically connected to the common doped region and the bit line is disposed over the substrate.───接触窗插塞电性连接至共用掺杂区域，且位线配置于基底上。

英语使用场景

Moreover, the resistive memory element is connected between the contact plug and the bit line.

The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.

In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation.

The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element.

The state of the memory element can thereby be detected by a voltage comparator sense amplifier that is connected to the bit line.

The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line.

This ensures that during read determination operation in the next read cycle, the potential of a selected bit line will not vary with the bit line residual discharge in the previous read cycle.

A memory device having an off-current (Ioff) robust precharge control circuit and a bit line precharge method are provided.