boundary scan信息详情
[计]边界扫描
boundary───n.边界；范围；分界线
boundary line───边界线；疆界线；受恩的，义务的; 界线
collision boundary───碰撞边界
obed boundary───obed边界
scan it───扫描一下
boundary rider───n.牧场巡修围栏工人
divergent boundary───[海洋][地质]离散边界
boundary condition───边界条件，极限条件；[数]边界条件，界面条件
diathermal boundary───透热边界
As a kind of new developing BIT technology, Boundary scan technology is widely used in industry.───边界扫描技术作为一种新兴的BIT技术，在工业界内得到了广泛的应用。
Some problems in logic cluster boundary scan test could not be neglected.───逻辑簇的边界扫描测试存在一些不可忽视的重要问题。
There are some common methods of design for testability, such as boundary scan test and so on.───目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
Therefore the method making use of boundary scan structure to carry out a debugging on system arises at the historic moment.───因此利用边界扫描结构来对系统进行调试的方法应运而生。
Boards with limited electrical access (including boundary scan) require higher emphasis on automated inspection.───带有有限电路包括边界扫描的印板更强调自动检测。
Boundary-scan technology (BST) is a new and effective way of test and design-for-testability ( DFT ) for VLSI circuits.───边界扫描技术是一种新型的VLSI电路测试及可测性设计方法。
Grand scale IC chip that every important company produces at present is almost all having the boundary scan structure.───并且目前各大公司生产的超大规模集成电路芯片基本全部具有边界扫描结构。
Fault injection emulation platform based on Joint Test Action Group(JTAG) boundary scan and dynamic partial reconfiguration is proposed.───提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。
At first this thesis gives the background and current situation of the boundary scan technology.───本文首先阐述了边界扫描技术产生的背景以及发展现状。
Meanwhile, how to control the boundary scan bus is mentioned in this paper. As in usual, most devices have no JTAG test access ports, the techniques discussed in this paper are valu...
With the continual improvement of the chip's integration level and complexity of print circuit board, the application of boundary scan test technology becomes wider and wider in testing ICs.
Aiming at the defects of BIT system in one new type airborne radar, this paper presents a board level BIT test technique based on boundary scan.
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
Based on the research of boundary scan and cluster test, a cluster test system is designed with test Bus controller chip, then it is verified with the GNS algorithm of W-A.
Users can use this boundary - scan master controller to complete boundary scan test more expediently and efficiently.