gate level信息详情
门水平
gate───vt.给…装大门；n.(Gate)人名；(英)盖特；(法、瑞典)加特；n.大门；出入口；门道
level───n.水平；标准；水平面；vt.使同等；对准；弄平；adj.水平的；平坦的；同高的；n.(Level)人名；(法)勒韦尔；vi.瞄准；拉平；变得平坦
gate chalk───门粉笔
la gate───拉门
arrival gate───到达口；下机门
festinate gate───festinate门
cow gate───在公地上放牧一头牛的权利
pearly gate───珍珠门
colline gate───柯林斯门
Using gate level modeling might not be a good idea for any level of logic design.───使用门级建模对于任何逻辑设计都不是一个好的设计。
Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping.───高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余。
energy optimization methods in circuit level and gate level have been investigated widely.───线路层、门层等低层能量优化方法已经得到广泛研究。
Most CAD tools allow IP verification to be performed by simulating the IP cores at register transfer level (RTL) or at the gate level [4].───多数CAD工具允许IP证明由模仿进行IP核心在记数器调动水平（RTL）或在门水平[4]。
each student completes a gate-level design for a RISC processor during the semester.───每一位学生必需在本学期完成一个逻辑闸级的简单指令集计算机（RISC）处理器设计。
All of these bring the challenge to the traditional gate-level test.───这些现状都带来了对传统门级测试的挑战，发展高层测试迫在眉睫。
Combined Novel Gate Level Model and Critical Primary Input Sharing for Genetic Algorithm Based Maximum Power Supply Noise Estimation───基于最大电源噪声门级模型的遗传算法电源噪声估计
Multi-objective Adaptive Genetic Algorithm for Gate-Level Evolution of Logic Circuits───基于多目标自适应遗传算法的逻辑电路门级进化方法
Optimization of Explicit Redundancy in Gate-Level Technology Mapping───门级工艺映射中显式冗余的优化
The verification includes RTL simulation, gate level simulation and static timing analysis.
And the process of functional verification consists of the implementation of RTL (register transfer level) simulation, gate level simulation and post-layout simulation in the process of design.
This thesis has accomplished the design of register transfer level (RTL) of every unit in the digital processing module, and passed function verification, logic synthesis, and gate level verification.
In VLSI design, gate level fault simulation is often too slow to meet the demand of time- to-market. Thus the register transfer level (RTL) fault simulation has become a hot topic recently.
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.