full adder发音

意思翻译

[计]全加器

全加法器

相似词语短语

adder───n.蝰蛇（欧洲产的小毒蛇）；加算器；猪鼻蛇（北美产无毒的）

death adder───致死毒蛇

enervated adder───能化加法器

watermark adder───水印加法器

full───n.全部；完整；adj.完全的，完整的；满的，充满的；丰富的；完美的；丰满的；详尽的；adv.十分，非常；完全地；整整；vt.把衣服缝得宽大

full height───全高度；由楼面至天花板

full throttle───加足马力；全节流；全节流，全开风门

full word───实词；全字

full monty───光猪六壮士（电影名，TheFullMonty）；n.一应俱全；一样不缺

双语使用场景

We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.───在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。

presented in this paper are then demonstrated on the design of an ECL 1-bit full adder.───提出的方法已用一位全加器的设计实例予以演示。

Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic.───二进制加减法，全加器实现及其性能，高速加法，带符号算术运算。

Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic.───二进制加减，全加器的实现和性能，高速加法，带符号加法。

at last, implement a full adder as the example.───最后，作为设计实例实现了一个异步全加器的设计。

Research on the algorithm of a corrected quantum full adder───量子全加法器的修改和算法研究

A Full Adder Realization with Complementary Single-Electron Transistors───一种基于互补型单电子晶体管的全加器电路设计

A Novel Full Adder Implementation Using Quantum Cellular Automata───基于量子细胞自动机的全加器实现

英语使用场景

Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic.

In this paper, we present a polarization-encoded optical full adder by using an inverse vector realized by transmissive feedback.

Wish you will love sentencedict.com and make progress everyday!

We take the Full Adder as an example to introduce the use of VHDL in the design of digital system, the experiment of digital circuit and the teaching.

Full adders are discussed, and a multiplexer based full adder is designed.

We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.

A model of algorithm has been proposed for composite neural network and the classification results of high precision are obtained through a full adder (FA) fostered by the model.

The practicability of the system is validated by implementing the simulation of a one-bit full adder based on FPGA.

The ideas presented in this paper are then demonstrated on the design of an ECL 1-bit full adder.