floating-point adder信息详情

floating-point adder发音

意思翻译

浮点加法器

相似词语短语

floating point───浮点,浮点法,浮点小数点;[计]浮点

floating point overflow───浮点溢出

adder───n.蝰蛇(欧洲产的小毒蛇);加算器;猪鼻蛇(北美产无毒的)

invalid floating point operation───浮点运算无效

floating───v.漂浮(float的现在分词);adj.流动的;漂浮的,浮动的

floating point division by zero───浮点除零

floating shelves───浮动货架

death adder───致死毒蛇

floating restaurants───浮动餐厅

双语使用场景

structure and logical designing, we get a high-speed and effective LOD circuit, which applied in floating-point adder.───我们从LOD的组成结构和逻辑两个方面进行设计,实现了一种快速、高效的LOD电路。

Floating-point Adder is a critical part in the coprocessor, which is attached to the computing basis of floating-point instructions.───浮点加法器是协处理器的核心运算部件,是实现浮点指令各种运算的基础,其设计优化是提高浮点运算速度和精度的关键途径。

Floating-point adder is one of the basic parts of CPU. Its performance has a direct effect on CPU floating-point processing capacity.───浮点加法器是构成CPU的基本部件之一,其性能优劣将直接影响CPU浮点处理能力。

Design and Optimization of a Fast Floating Point Adder───一种快速浮点加法器的设计与优化方法

Optimized Design of a Fast Floating-point Adder───快速浮点加法器的优化设计

The FPGA Implementation of the Triple Data-path Floating-point Adder───三数据通道浮点加法器的FPGA实现

Full-custom Implementation of Fast Floating-point Adder───快速浮点加法器的全定制设计

The Combined Design of the Three Carry Propagation in the Floating- Point Adder───浮点加法器中进位传递问题的合并处理

On the Multi-Input Floating-Point Adder Algorithm───多输入浮点加法器算法研究

英语使用场景

Floating-point adder is one of the basic parts of CPU. Its performance has a direct effect on CPU floating-point processing capacity.

High-Speed Floating-point Adder is a critical part in the coprocessor, which is attached to the computing basis of floating-point instructions.

The speed of floating-point adder is important factor for DSP performance. The speed of LOD is key factor for floating-point adder performance.

Through the structure and logical designing, we get a high-speed and effective LOD circuit, which applied in floating-point adder.

The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.

The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.