clock line发音

意思翻译

时钟线

相似词语短语

clock───vt.记录；记时；n.(Clock)人名；(英)克洛克；n.时钟；计时器；vi.打卡；记录时间

line line───线条线条

twelveo clock───十二点钟

electric clock───[仪]电钟

pelvic clock───骨盆时钟

o clock───n.点钟

speaking clock───n.电话报时服务

sextant clock───六分仪钟

gpu clock───gpu时钟

双语使用场景

The host changes the data line only when the Clock line is low, and data is read by the device when Clock is high.───只有当时钟线为低的时候，主机才可以改变数据线(也就是将数据写入到数据线)。数据将在时钟为高电平的时候被设备读龋。

The host has ultimate control over the bus and may inhibit communication at any time by pulling the Clock line low.───主机对总线有最高的控制权，在任何时候通过将时钟线拉低就可以禁止通信。

In a preferred embodiment, this estimation is made by identifying a best clock line between the first and second convex hulls.───在优选实施例中，通过识别第一和第二凸包之间的最佳时钟线来进行此估计。

The system raises the 'clock' line to allow the next transmission.───系统拉高时钟将允许下一次传输。

If the device finds the system holding the 'clock' line inactive, the transmission is terminated.───如果设备发现主机系统将电平拉低，就终止传输。

The auxiliary device checks the 'clock' line. If the line is inactive, output from the device is not allowed.───辅助设备（指键盘）检查时钟线，如果时低电平，禁止发送数据。

The auxiliary device checks the 'clock' line during the transmission at intervals not exceeding 100 microseconds.───设备在传输过程中检查时钟线间隔不超过100us。

英语使用场景

When the keyboard or mouse wants to send information, it first checks the Clock line to make sure it's at a high logic level.

Results indicate that when fault duration is shorter than phase difference of three clocks, enhanced ST-TMR can almost mask the SEU in combinational logic circuit and clock line.