chip level发音

意思翻译

片级

相似词语短语

crisper chip───脆片

chip shot───打高球；近穴击球；削球；n.[体]近穴击球

potato chip───n.炸土豆片

chip dale───奇普戴尔

chip ingram───芯片ingram

chip gaines───奇普·盖恩斯

said chip───奇普说

computer chip───电脑芯片

level───n.水平；标准；水平面；vt.使同等；对准；弄平；adj.水平的；平坦的；同高的；n.(Level)人名；(法)勒韦尔；vi.瞄准；拉平；变得平坦

双语使用场景

loosely-coupled architecture being scaled down to the chip level.───其看作松耦合架构按比例缩小至芯片级。

They can be classified into wafer level, chip level, and package level stacking.───它们可以分为圆片级封装、芯片级封装、和封装面。

We clearly demonstrated that we can do it at the unit chip level," says Kim.───金说“我们证实了我们可以在单元芯片级做到这个。”

The deployment comes a year after ETH and IBM scientists announced plans to collaborate on chip-level water-cooling and energy reuse.───这项研究于1年前开始，当时ETH和IBM的科学家宣布他们计划合作研究芯片级水冷及能源循环利用的项目。

The advantages of this chip-level spring damping structure are one integrated, good consistency and engineering applications.───该芯片级弹簧减震结构具有一次集成、一致性好、易于组阵、工程应用方便等特点。

Today, chip-level multiprocessing provides more CPUs on a single chip, permitting even greater performance due to reduced memory latency.───现在，芯片级多处理能够在单个芯片上提供更多的CPU，由于减少了内存延迟，因而可获得更高的性能。

This paper mainly discusses on the evolving three - dimensional integration technology of silicon - based chip - level electronics.───本文围绕目前电子封装业正在兴起的硅基芯片级三维集成技术展开论述。

Tightly-coupled multiprocessing refers to chip-level multiprocessing (CMP).───紧密耦合多处理指芯片级多处理（CMP）。

Performs block level and full chip level simulations using logic and mixed-signal simulators.───按照逻辑和混合信号仿真原则进行模块和芯片级的仿真。

英语使用场景

Module level micro architecture design and RTL implementation. Chip level integration.

With the support of advanced EDA tools and chip level verification environment, in this paper, the code coverage analysis and statistic job for NSR module are also done.

It can satisfy the requirement of digital plugboard test and carry out the plugboards test to chip level. Thus it has wide application potential.

In the LED chip level, how to maintain the internal quantum efficiency under high current injection is a big challenge for the material engineering.

They can be classified into wafer level, chip level, and package level stacking.

Think about the loosely-coupled architecture being scaled down to the chip level.