chip area发音

意思翻译

切屑通道；基片面积

相似词语短语

crisper chip───脆片

chip shot───打高球；近穴击球；削球；n.[体]近穴击球

potato chip───n.炸土豆片

chip dale───奇普戴尔

chip ingram───芯片ingram

chip gaines───奇普·盖恩斯

said chip───奇普说

computer chip───电脑芯片

mint chip───薄荷片

双语使用场景

Thus, software radio DDFS based on CORDIC algorithm can help to reduce chip area, power dissipation and cost.───所以CORDIC算法来实现软件无线电直接数字频率合成器有助于节省芯片面积、降低功耗、减少成本。

Thus, only a very small extra chip area is required even if full scan design is used.───这样，即使采用全扫描设计，也仅需较小的芯片面积。

Its circuit structure is very complex and its chip area is restricted severely by the client.───其电路结构十分复杂，而且客户又对版图面积做了详细的规定。

Since this year, show couplet to ever also expressed publicly to there can be a few significant progresses in chip area for many times.───本年以来，闪联也曾屡次暗地暗示在芯片区域会有一些主要进展。

These CAN controllers require a greater chip area, however, and are therefore more expensive.───因此这些可能控制器要求一个更加巨大的芯片区域，然而，并且是更加昂贵的。

To a commercial chip, area is a crucial factor, because the price of chip is decided by it.───在芯片的商业应用中，面积决定了芯片的价格，更是芯片生命力的决定因素。

Because the circuit is simple, the tuning circuit has less chip area and less power consumption.───因为比较简单的电路，这个电路有较小的晶片面积和较低的能量损耗。

英语使用场景

This flip-flop has correct logic function as a dynamic D flip-flop, and has the distinct advantage of simple structure, small chip area, and simple two-phase clock.

The divider based on a dual-modulus prescaler and pulse-swallow counter is designed to reduce power consumption and chip area.

Because the circuit is simple, the tuning circuit has less chip area and less power consumption.

Also, the added schottky diode can be easily realized by schottky contact in the drain of the NMOSFET, which does not add chip area.

By using a ring voltage controlled oscillator(VCO), chip area and production cost were saved.

The invention can effectively position a defect memorizer without increasing the chip area, and is convenient for defect analysis and design improvement.

On the aspect of chip architecture, considering the factors such as parallelizable of hardware, utilization of memory and chip area, we embodied 9 scan engines on chip to realize the multi-scan.

A charge scaling D/A converter with capacitor voltage divider is designed, which extends the resolution of a parallel D/A converter as well as reduces the chip area greatly.

Thus, only a very small extra chip area is required even if full scan design is used.