two-phase clock信息详情
两相时钟
phase───vt.分阶段进行;使定相;n.月相;时期,阶段
clock───vt.记录;记时;n.(Clock)人名;(英)克洛克;n.时钟;计时器;vi.打卡;记录时间
two two───22
anacrotic phase───无核期
rebellious phase───叛逆期
venous phase───[医]静脉相
phase loss───失相
phase transition───[物]相变
aqueous phase───[冶]水相
The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.───差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整,实现了两路AD的等间隔采样。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.───在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
To test for this scenario, rig up an external phase-locked dual-clock source with a knob that intentionally adjusts the phase relationship of the two clocks.───为了测试这个,做一个外部相位锁定的双时钟源,带有两个时钟有意调节相位关系的节点。
The two-phase clock signal for the delay line is provided by a matching clock generator chip.
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
This flip-flop has correct logic function as a dynamic D flip-flop, and has the distinct advantage of simple structure, small chip area, and simple two-phase clock.
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