transfer level发音

意思翻译

传输级别

相似词语短语

transfer───v.转让；转接；移交；转移（地方）；（使）换乘；转存，转录；调动（工作）；传染，传播；使（运动员）转队；把（钱）转到另一账户，机构上；n.（地点的）转移；（工作的）调动；已调动的人或东西；权力的移交；运动员转会；（公共汽车、飞机等的）转移；（财产的）转让；数据的拷贝；图画，图案；转车票

level───n.水平；标准；水平面；vt.使同等；对准；弄平；adj.水平的；平坦的；同高的；n.(Level)人名；(法)勒韦尔；vi.瞄准；拉平；变得平坦

transfer paper───n.摹写纸

transfer station───图像转移设备；传送站；传输站

mail transfer───信汇，邮汇

transfer case───分动箱，变速箱；分动器，分动箱；变速箱

mouthfuls transfer───口转移

custody transfer───运输监护；密闭输送

embryo transfer───胚胎移植；胚胎转移；胚胎植入；胚泡移植

双语使用场景

main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).───行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。

The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.───寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。

Generally the higher quality of labor force, the transfer speed is faster than the lower quality of labor, while the transfer level is higher.───一般劳动力素质高者，转移速度要快于劳动力素质低者，同时转移层次也较高。

We base on it to establish abstract model between the sequential executable codes and the register transfer level (RTL) description.───我们依该方法在循序可执行程式码和暂存器传输层级间建立抽象模型。

Most CAD tools allow IP verification to be performed by simulating the IP cores at register transfer level (RTL) or at the gate level [4].───多数CAD工具允许IP证明由模仿进行IP核心在记数器调动水平（RTL）或在门水平[4]。

High Level Synthesis Method for Clustered Register Transfer Level Architecture───面向分模块寄存器传输级结构的高层次综合方法

The construction process control of high level building structure transfer-level───高层建筑结构转换层施工过程控制

Register-Transfer Level Mapping Algorithms for Memories───寄存器传输级存储器工艺映射算法

machines should be installed after the transfer level;───用户注意事项：1，机器安装后应调水平；

英语使用场景

And the process of functional verification consists of the implementation of RTL (register transfer level) simulation, gate level simulation and post-layout simulation in the process of design.

The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).

The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.

In VLSI design, gate level fault simulation is often too slow to meet the demand of time- to-market. Thus the register transfer level (RTL) fault simulation has become a hot topic recently.

We base on it to establish abstract model between the sequential executable codes and the register transfer level (RTL) description.

RTL(register transfer level) functional verification system for package assembly function in IPOA application is illustrated in this paper.

The influence of architectures on synthesis methods is discussed, and a clustered register transfer level architecture as object architecture is presented.

The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.

This thesis has accomplished the design of register transfer level (RTL) of every unit in the digital processing module, and passed function verification, logic synthesis, and gate level verification.