timing analysis发音

意思翻译

[计]定时分析

相似词语短语

analysis───n.分析；分解；验定

timing differences───时间性差异

statement analysis───n.财务报表分析；财务报表分析；决算表分析

forenoon timing───上午时间

timing chain───[仪]定时链

wronging timing───错误的时间

conjoint analysis───联合分析；组合分析；结合分析

timing diagram───计时图；时间图；正时图，定时图

valve timing───[机]气门正时；[机]阀定时

双语使用场景

A tool for timing analysis of UML sequence diagrams is described in this paper.───文章描述了一个对带时间约束的UM L序列图进行分析的工具。

The timing analysis in the design of digital integrated circuits is described.───文章对数字集成电路设计中的时序分析作了一个概要的介绍。

Implementation of static timing analysis.───静态时序分析的实现。

Understanding of the concept of timing. Able to perform static timing analysis.───具备时序概念，能进行静态时序分析。

A new statistical model of gate delay and a new statistical static timing analysis method are proposed.───提出了一种新的门单元延迟的统计分析模型和一种新的统计静态时序分析方法。

familiar with ic developing environments including logic synthesis, timing analysis and verilog simulation.───熟悉逻辑综合，时序分析，verilog仿真等ic开发环境。

Experience with Industry standard design tools for RTL synthesis and timing analysis required.───经验和行业标准设计，工具和时序分析需要RTL合成。

Based on the layout static timing analysis, the clock period was optimized by the clock skew scheduling utilizing the DCCB.───利用此特性，基于电路版图时序分析，通过重构DCCB单元进行时钟偏差调整，优化时钟周期。

Delay look-up table(LUT) of standard logic circuits are useful in applications such as auto - synthesis and static timing analysis.───门电路延时参数的查找表在电路逻辑综合及静态时序分析中均有重要应用。

英语使用场景

The verification includes RTL simulation, gate level simulation and static timing analysis.

Wire wrap large white pearls with BRIGHT silver wire. Please make timing analysis as your work them.

The article presents some concepts of the post route timing analysis in HDL design and then introduces the usage of the Static Timing Analysis tool TIMING ANALYZER of MAXPLUSII.

Based on the layout static timing analysis, the clock period was optimized by the clock skew scheduling utilizing the DCCB.

We also triad to apply the new timing analysis method to X - ray binaries.

Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.